1. Field of the Invention
This invention relates to a static semiconductor memory device, and more particularly to a SRAM using MOS transistors.
2. Description of the Prior Art
The MOS SRAM memory cell comprises a flip-flop constructed of two (first and second) inverters with inputs and outputs cross-connected. The output (storage node) of each inverter is connected through a transfer MOSFET to a different bit line. The respective gate electrodes of both transfer MOSFETs are connected to the same word line. Each inverter is composed of a drive MOSFET and a load element. The four MOSFETs are of n-channel type. Each load element consists of a high resistance element, p-channel MOSFET, or the like. Each p-channel MOSFET consists of a polysilicon thin-film transistor (referred to as TFT). If headed with the terms "the first" or "the second", those are implied to be associated with the first or second inverter, hereinafter.
Assuming that after the data write into a memory cell, the first storage node of it is at "HIGH" level and the second storage node at "LOW" level, the data read from the memory cell is carried out by charging the potential on the first and second bit lines to the supply voltage, and turning on the first and second transfer MOSFETs. To prevent the data stored in the memory cell from being damaged, the first drive MOSFET must remain "off" and the second drive MOSFET "on".
In the high-resistance load type MOS SRAM, the potential of the second storage node must be up to the threshold voltage of the first drive MOSFET. The potential of the second storage node is determined on the quotient of the difference between supply voltage and ground potential by the on-resistances of the second transfer and drive MOSFETs. Hence the smaller, the better the on-resistance of the second drive MOSFET is while the greater, the better the on-resistance of the second transfer MOSFET. The drive MOSFETs are the same in structure as the transfer MOSFETs except in length and width of channel. The on-resistance of the MOSFET is proportional to the channel length and inversely proportional to the channel width. In order to prevent data damage by keeping the "LOW" storage node potential as it is during readout, therefore the shorter and wider the channel is, the better the drive MOSFET is while the longer and narrower the channel is, the better the transfer MOSFET is. Thus the channel length of the drive MOSFETs and the channel width of the transfer MOSFETs are designed to the respective minimum processible sizes. The channel width of the drive MOSFETs and the channel length of the transfer MOSFETs are designated to be greater than the respective processible sizes. This stands in the way of realization of less area memory cells.
In addition, in the TFT load type MOS SRAM, the potential of the second storage node must be up to logic threshold value of the first inverter. In general ICs as the logic threshold value of the CMOS inverter is usually selected to be about half the supply voltage. On the other hand for TFT load type MOS SRAM it is not so. Since the gain (factor) of the p-channel TFT is as small as about 1/100 that of the same-size drive MOSFET (bulk MOSFET), it follows that the logic threshold value of the inverters constituting a flip-flop is not so different from the threshold voltage of the drive MOSFETs: For example, it becomes about 0.87 V when the threshold voltage of the drive MOSFET is 0.7 V. There are therefore similar problems to those with the high resistance load type MOS SRAM.